Performance of data storage systems depends on the relative speed of the data storage technology used to implement the system (access time), and on the processor overhead of operations to read, write and move data within the system (processing speed). To improve access time, data storage systems utilize fast memory technology to “cache” frequently accessed data. In balancing access time and cost, some data storage systems utilize stratifications of data storage technology; these stratifications are commonly referred to as “tiers.” A cache may have a fast and a slow tier, and a persistent data storage device may have a fast and a slow tier. In a data storage system having a cache with a fast tier, the cache may have an access time commensurate with the processing speed such that data access operations limited to the cache do not appreciably limit the performance of the processor. In those same systems, access times for persistent data storage devices may be orders of magnitude slower, so any data access operation that includes a persistent data storage device may severely limit the performance of the processor by forcing the processor to remain idle for periods of time, and therefore unable to service data access requests.
Data storage systems may attempt to alleviate the problems caused by slow persistent data storage access time by introducing a second processor to service data access requests. In such systems, data access requests may be assigned to any processor that is not currently servicing data access requests. However, multiple processors servicing data access requests introduces the possibility that each processor may attempt to manipulate the same data, thereby requiring data integrity protection mechanisms. Also, each of the multiple processors may still be idled if multiple data access requests all require access to persistent data storage.
Consequently, it would be advantageous if an apparatus existed that is suitable for load balancing tier specific data access operations in a tiered data storage system having multiple processors.